1. Field of the Invention
The present invention relates to a semiconductor device, in particular, a semiconductor device that reduces a leakage current of a transistor.
2. Description of the Background Art
Examples of a technique of reducing a leakage current of a transistor may include an MTCMOS (Multi Threshold Voltage Complementary Metal Oxide Semiconductor) circuit that reduces a leakage current in a standby state, and a VTCMOS (Variable Threshold Voltage Complementary Metal Oxide Semiconductor) circuit that reduces a leakage current in an operating state.
As one example of the MTCMOS circuit, for example, Japanese Patent Laying-Open No. 11-284493 discloses the following configuration. That is, in a master-slave flip-flop including a master flip-flop and a slave flip-flop, the master flip-flop is an inverter constituted of a transistor having a low threshold value and connected to a power supply which can be interrupted. Thus, it is possible to suppress power consumption in a standby state and, also, to suppress reduction in operating speed. Moreover, the slave flip-flop is an inverter constituted of a transistor having a relatively higher threshold value so as to drive an output. Thus, a leakage current becomes small in amount. Therefore, the flip-flop can be operated normally even in the standby state. As a result, there is no possibility that stored data is lost.
As another example of the MTCMOS circuit, for example, Japanese Patent Laying-Open No. 2002-110920 discloses the following configuration. That is, two combinational circuits are a logic circuit constituted of a transistor having a low threshold voltage, and a transistor connected between this logic circuit and a power supply line and turned on and off in accordance with a control signal. This control signal makes the two combinational circuits active only when two flip-flop circuits connected to output ends of the two combinational circuits, respectively, capture data in accordance with the control signal. Accordingly, the combinational circuit receives electric power only when outputting data, but receives no electric power in other conditions, leading to reduction in leakage current.
As one example of the VTCMOS circuit, for example, Japanese Patent Laying-Open No. 2002-111470 discloses a configuration that a substrate bias control regulator makes a substrate voltage variable to suppress a leakage current and to achieve low power consumption.
However, the configuration disclosed in each of Japanese Patent Laying-Open Nos. 11-284493 and 2002-110920 is merely one example of the MTCMOS circuit and, therefore, is not intended to reduce a leakage current in an operating state. In the configuration disclosed in Japanese Patent Laying-Open No. 2002-110920, particularly, all transistors included in the logic circuit are operated constantly in an operating state, that is, when outputting data. Consequently, there arises a problem that if the flip-flop circuit is operated at a low speed, a rate of power consumption due to a leakage current with respect to power consumption in the operating state disadvantageously increases.
In addition, each of the configurations disclosed in Japanese Patent Laying-Open Nos. 11-284493, 2002-110920 and 2002-111470 requires an additional power supply line for controlling supply of electric power to a transistor. Consequently, there arises a problem that a semiconductor device disadvantageously increases in area.